A Low-Latency Reconfigurable Multistage Interconnection Network

This paper presents a low-latency multistage interconnection network. The proposed architecture features simplicity of design, a straightforward address encoding/decoding scheme, and provides non-blocking as well as multi-casting and broadcasting capabilities. It uses the latency-insensitive design methodology, a paradigm that eases the design process while ensuring correctness of data transfers. The design is tailored to multiprocessor reconfigurable devices. Our results show that the proposed interconnection has a small footprint, a very high throughput, and that it can operate at high clock frequencies (> 500kHz) on recent FPGAs both from Xilinx and Intel.