{"title":"可编程多级半带FIR抽取器，输入数据速率高达2.56 MSPS","authors":"T. Yoshida, H. Kobayashi","doi":"10.1109/IMTC.1990.66006","DOIUrl":null,"url":null,"abstract":"A multistage half-band FIR (finite impulse response) decimator has been implemented on a 40000-gate, 1.5- mu m CMOS gate array, which dissipates 1.5 W at a clock rate of 25.6 MHz (a sampling rate of 2.56 MHz). The filter handles 20-b, 2.56-M sample/s input data. It has been tested for frequency shifting and zooming in a prototype FFT (fast Fourier transform) spectrum analyzer and has increased the frequency resolution by up to 2/sup 17/ times without aliasing, resulting in frequency resolution on the order of 20 mHz; it has a 96-dB dynamic range.<<ETX>>","PeriodicalId":404761,"journal":{"name":"7th IEEE Conference on Instrumentation and Measurement Technology","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A programmable multistage half-band FIR decimator for input data rates up to 2.56 MSPS\",\"authors\":\"T. Yoshida, H. Kobayashi\",\"doi\":\"10.1109/IMTC.1990.66006\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A multistage half-band FIR (finite impulse response) decimator has been implemented on a 40000-gate, 1.5- mu m CMOS gate array, which dissipates 1.5 W at a clock rate of 25.6 MHz (a sampling rate of 2.56 MHz). The filter handles 20-b, 2.56-M sample/s input data. It has been tested for frequency shifting and zooming in a prototype FFT (fast Fourier transform) spectrum analyzer and has increased the frequency resolution by up to 2/sup 17/ times without aliasing, resulting in frequency resolution on the order of 20 mHz; it has a 96-dB dynamic range.<<ETX>>\",\"PeriodicalId\":404761,\"journal\":{\"name\":\"7th IEEE Conference on Instrumentation and Measurement Technology\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-02-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"7th IEEE Conference on Instrumentation and Measurement Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMTC.1990.66006\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"7th IEEE Conference on Instrumentation and Measurement Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMTC.1990.66006","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A programmable multistage half-band FIR decimator for input data rates up to 2.56 MSPS
A multistage half-band FIR (finite impulse response) decimator has been implemented on a 40000-gate, 1.5- mu m CMOS gate array, which dissipates 1.5 W at a clock rate of 25.6 MHz (a sampling rate of 2.56 MHz). The filter handles 20-b, 2.56-M sample/s input data. It has been tested for frequency shifting and zooming in a prototype FFT (fast Fourier transform) spectrum analyzer and has increased the frequency resolution by up to 2/sup 17/ times without aliasing, resulting in frequency resolution on the order of 20 mHz; it has a 96-dB dynamic range.<>
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