K. Lawson, G. Alvarez, S. Bayne, V. Veliadis, D. Urciuoli
{"title":"SiC JFET器件脉冲工作特性分析","authors":"K. Lawson, G. Alvarez, S. Bayne, V. Veliadis, D. Urciuoli","doi":"10.1109/PPC.2011.6191651","DOIUrl":null,"url":null,"abstract":"The purpose of this research is to investigate the performance of Silicon Carbide JFET for us in solid state circuit breakers. The device under test for these results is a research grade JFET with a rated blocking voltage of 1200V and a rated forward current of 10A with a power density of 200W/cm2. In order to drive the JFET device, a unique gate driver had to be designed and built to provide switching between two independent rail voltages. The gate driver had to be able to provide adjustable rail voltages with one rail ranging between 0V and −40V and the other rail going between 0V and 2.5V. The gate driver is completely isolated to operate on a high-side switch. In order to test these devices in pulsed switching applications a pulse ring down circuit was designed and built to provide a current pulse of 100A (10 times the rated current) with a charging voltage range between 100V and 500V. Special consideration had to be given to the design of this pulse ring down circuit in order to achieve a high di/dt, and therefore reach the target peak current levels.","PeriodicalId":331835,"journal":{"name":"2011 IEEE Pulsed Power Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Analysis of SiC JFET devices during pulsed operation\",\"authors\":\"K. Lawson, G. Alvarez, S. Bayne, V. Veliadis, D. Urciuoli\",\"doi\":\"10.1109/PPC.2011.6191651\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The purpose of this research is to investigate the performance of Silicon Carbide JFET for us in solid state circuit breakers. The device under test for these results is a research grade JFET with a rated blocking voltage of 1200V and a rated forward current of 10A with a power density of 200W/cm2. In order to drive the JFET device, a unique gate driver had to be designed and built to provide switching between two independent rail voltages. The gate driver had to be able to provide adjustable rail voltages with one rail ranging between 0V and −40V and the other rail going between 0V and 2.5V. The gate driver is completely isolated to operate on a high-side switch. In order to test these devices in pulsed switching applications a pulse ring down circuit was designed and built to provide a current pulse of 100A (10 times the rated current) with a charging voltage range between 100V and 500V. Special consideration had to be given to the design of this pulse ring down circuit in order to achieve a high di/dt, and therefore reach the target peak current levels.\",\"PeriodicalId\":331835,\"journal\":{\"name\":\"2011 IEEE Pulsed Power Conference\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE Pulsed Power Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PPC.2011.6191651\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Pulsed Power Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PPC.2011.6191651","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis of SiC JFET devices during pulsed operation
The purpose of this research is to investigate the performance of Silicon Carbide JFET for us in solid state circuit breakers. The device under test for these results is a research grade JFET with a rated blocking voltage of 1200V and a rated forward current of 10A with a power density of 200W/cm2. In order to drive the JFET device, a unique gate driver had to be designed and built to provide switching between two independent rail voltages. The gate driver had to be able to provide adjustable rail voltages with one rail ranging between 0V and −40V and the other rail going between 0V and 2.5V. The gate driver is completely isolated to operate on a high-side switch. In order to test these devices in pulsed switching applications a pulse ring down circuit was designed and built to provide a current pulse of 100A (10 times the rated current) with a charging voltage range between 100V and 500V. Special consideration had to be given to the design of this pulse ring down circuit in order to achieve a high di/dt, and therefore reach the target peak current levels.
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