A Current Domain Computing-in-Memory SRAM Macro with Hybrid IAF-SAR ADC for Signal Margin Enhancement

This paper presents a computing-in-memory (CIM) SRAM macro utilizing current domain computing for multiply-and-accumulate (MAC) operations. A 32x64 8T bitcell array is used to store the weight data. This design adopts the modulated word line pulse-width method to convert 4-bit digital input data to analog domain. The MAC operation of weight and input data is accomplished through bitwise multiplication and the result is transformed to current which accumulates on the reading bit line (RBL). In order to improve the signal margin without sacrificing the readout precision, a hybrid integrate-and-fire (IAF)-SAR ADC is proposed to convert the computing result into digital domain. The presented design is implemented in a standard 65nm CMOS process and simulation results indicate the proposed 32x64 CIM macro achieves energy efficiency of 18.76 TOPS/W and peak throughput of 10.24 GOPS with 4-bit inputs and 4-bit weights.