{"title":"一个1.5MS/s的6位ADC, 0.5V电源","authors":"S. Gambini, J. Rabaey","doi":"10.1109/ASSCC.2006.357848","DOIUrl":null,"url":null,"abstract":"A moderate resolution analog-to-digital converter targeting wireless sensor networks applications is presented. Employing a successive approximation architecture, the device achieves 6 bits of resolution at 1.5 MS/s output rate, while drawing 28muA from a low 0.5 V supply, corresponding to a Figure of Merit (FOM) of .25pJ/conversion step. Low-density metal5-metal6 capacitors guarantee feedback DAC linearity while minimizing input capacitance, while the use of a passive sample and hold, combined with a class-AB comparator reduce analog power dissipation to 4muW (30% of the total). The analog core is operational for supply values as low as .3V, even though sampling rate is reduced to 175kS/s.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"A 1.5MS/s 6-bit ADC with 0.5V supply\",\"authors\":\"S. Gambini, J. Rabaey\",\"doi\":\"10.1109/ASSCC.2006.357848\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A moderate resolution analog-to-digital converter targeting wireless sensor networks applications is presented. Employing a successive approximation architecture, the device achieves 6 bits of resolution at 1.5 MS/s output rate, while drawing 28muA from a low 0.5 V supply, corresponding to a Figure of Merit (FOM) of .25pJ/conversion step. Low-density metal5-metal6 capacitors guarantee feedback DAC linearity while minimizing input capacitance, while the use of a passive sample and hold, combined with a class-AB comparator reduce analog power dissipation to 4muW (30% of the total). The analog core is operational for supply values as low as .3V, even though sampling rate is reduced to 175kS/s.\",\"PeriodicalId\":142478,\"journal\":{\"name\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2006.357848\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357848","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A moderate resolution analog-to-digital converter targeting wireless sensor networks applications is presented. Employing a successive approximation architecture, the device achieves 6 bits of resolution at 1.5 MS/s output rate, while drawing 28muA from a low 0.5 V supply, corresponding to a Figure of Merit (FOM) of .25pJ/conversion step. Low-density metal5-metal6 capacitors guarantee feedback DAC linearity while minimizing input capacitance, while the use of a passive sample and hold, combined with a class-AB comparator reduce analog power dissipation to 4muW (30% of the total). The analog core is operational for supply values as low as .3V, even though sampling rate is reduced to 175kS/s.
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