Nurqamarina Binti Mohd Noor, Yusrina Yusof, A. Saparon
{"title":"同步SRAM的低面积fsm存储器BIST","authors":"Nurqamarina Binti Mohd Noor, Yusrina Yusof, A. Saparon","doi":"10.1109/CSPA.2009.5069261","DOIUrl":null,"url":null,"abstract":"As the memory enters submicron technology, new test algorithm that will be able to give a better fault coverage such as to detect all intra-word coupling fault (CF) has been widely developed. In order to implement this algorithm to the memory, test technique such as BIST is utilized. Common types of memory built-in-self test (MBIST); microcode-based MBIST and FSM-based MBIST. The popular approach of designing various kind of MBIST architectures are either by targeting to reach specific testing requirement such as on full speed and at speed or by considering the cost-constraint and area overhead such low-cost or low-area design. In this paper, FSM-based BIST is designed to be able detecting all intra-word coupling fault (CF) in a synchronous SRAM under low- area constraint of test requirement.","PeriodicalId":338469,"journal":{"name":"2009 5th International Colloquium on Signal Processing & Its Applications","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Low area FSM-based memory BIST for synchronous SRAM\",\"authors\":\"Nurqamarina Binti Mohd Noor, Yusrina Yusof, A. Saparon\",\"doi\":\"10.1109/CSPA.2009.5069261\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As the memory enters submicron technology, new test algorithm that will be able to give a better fault coverage such as to detect all intra-word coupling fault (CF) has been widely developed. In order to implement this algorithm to the memory, test technique such as BIST is utilized. Common types of memory built-in-self test (MBIST); microcode-based MBIST and FSM-based MBIST. The popular approach of designing various kind of MBIST architectures are either by targeting to reach specific testing requirement such as on full speed and at speed or by considering the cost-constraint and area overhead such low-cost or low-area design. In this paper, FSM-based BIST is designed to be able detecting all intra-word coupling fault (CF) in a synchronous SRAM under low- area constraint of test requirement.\",\"PeriodicalId\":338469,\"journal\":{\"name\":\"2009 5th International Colloquium on Signal Processing & Its Applications\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-03-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 5th International Colloquium on Signal Processing & Its Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSPA.2009.5069261\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 5th International Colloquium on Signal Processing & Its Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSPA.2009.5069261","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low area FSM-based memory BIST for synchronous SRAM
As the memory enters submicron technology, new test algorithm that will be able to give a better fault coverage such as to detect all intra-word coupling fault (CF) has been widely developed. In order to implement this algorithm to the memory, test technique such as BIST is utilized. Common types of memory built-in-self test (MBIST); microcode-based MBIST and FSM-based MBIST. The popular approach of designing various kind of MBIST architectures are either by targeting to reach specific testing requirement such as on full speed and at speed or by considering the cost-constraint and area overhead such low-cost or low-area design. In this paper, FSM-based BIST is designed to be able detecting all intra-word coupling fault (CF) in a synchronous SRAM under low- area constraint of test requirement.