带拓扑约束的微电子验证库电路中的采样等功能信号开关

2017 IEEE National Aerospace and Electronics Conference (NAECON) Pub Date : 2017-06-01 DOI:10.1109/NAECON.2017.8268800

L. A. Hsia, G. Vernizzi, M. Lanzerotti, D. Langley

{"title":"带拓扑约束的微电子验证库电路中的采样等功能信号开关","authors":"L. A. Hsia, G. Vernizzi, M. Lanzerotti, D. Langley","doi":"10.1109/NAECON.2017.8268800","DOIUrl":null,"url":null,"abstract":"This paper extends a methodology for microelectronics verification to the situation in which signal switches are applied to library circuits containing INV, NAND2, NOR2, NAND3, and NOR3 gates. Monte Carlo methods are used to sample the frequency distributions of the topological genus of library circuits including a 4-bit adder.","PeriodicalId":306091,"journal":{"name":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Sampling iso-functional signal switches in library circuits for microelectronics verification with topological constraints\",\"authors\":\"L. A. Hsia, G. Vernizzi, M. Lanzerotti, D. Langley\",\"doi\":\"10.1109/NAECON.2017.8268800\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper extends a methodology for microelectronics verification to the situation in which signal switches are applied to library circuits containing INV, NAND2, NOR2, NAND3, and NOR3 gates. Monte Carlo methods are used to sample the frequency distributions of the topological genus of library circuits including a 4-bit adder.\",\"PeriodicalId\":306091,\"journal\":{\"name\":\"2017 IEEE National Aerospace and Electronics Conference (NAECON)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE National Aerospace and Electronics Conference (NAECON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NAECON.2017.8268800\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE National Aerospace and Electronics Conference (NAECON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.2017.8268800","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文将微电子验证方法扩展到信号开关应用于包含INV, NAND2, NOR2, NAND3和NOR3门的库电路的情况。采用蒙特卡罗方法对包含4位加法器的库电路的拓扑格的频率分布进行了采样。

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Sampling iso-functional signal switches in library circuits for microelectronics verification with topological constraints

This paper extends a methodology for microelectronics verification to the situation in which signal switches are applied to library circuits containing INV, NAND2, NOR2, NAND3, and NOR3 gates. Monte Carlo methods are used to sample the frequency distributions of the topological genus of library circuits including a 4-bit adder.

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2017 IEEE National Aerospace and Electronics Conference (NAECON)

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