Seongwoong Lim, Wasanthamala Badalawa, M. Fujishima
{"title":"110GHz无电感CMOS分频器","authors":"Seongwoong Lim, Wasanthamala Badalawa, M. Fujishima","doi":"10.1109/ASSCC.2009.5357179","DOIUrl":null,"url":null,"abstract":"An inductor-less 110GHz ring-type frequency divider (RILFD) has been proposed. Body-injection and biasing technique have been adopted to achieve high speed and divide-by-three operation and fine tuning of operation frequency. The RILFD was fabricated by a 1P12M 65nm bulk CMOS process. The core size is 10.8×8.5μm2. The locking range is 9.1%, from 100.8 to 110.4GHz, under varying of body-bias voltage from −0.2V to 0.4V. The RILFD consumes 4.5mW at the supply voltage of 1V excluding an output buffer. The output phase noise is −117.6dBc/Hz at 1MHz offset. This work has been achieved the smallest core size among frequency dividers reported to date operating over 100GHz.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 110GHz inductor-less CMOS frequency divider\",\"authors\":\"Seongwoong Lim, Wasanthamala Badalawa, M. Fujishima\",\"doi\":\"10.1109/ASSCC.2009.5357179\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An inductor-less 110GHz ring-type frequency divider (RILFD) has been proposed. Body-injection and biasing technique have been adopted to achieve high speed and divide-by-three operation and fine tuning of operation frequency. The RILFD was fabricated by a 1P12M 65nm bulk CMOS process. The core size is 10.8×8.5μm2. The locking range is 9.1%, from 100.8 to 110.4GHz, under varying of body-bias voltage from −0.2V to 0.4V. The RILFD consumes 4.5mW at the supply voltage of 1V excluding an output buffer. The output phase noise is −117.6dBc/Hz at 1MHz offset. This work has been achieved the smallest core size among frequency dividers reported to date operating over 100GHz.\",\"PeriodicalId\":263023,\"journal\":{\"name\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2009.5357179\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357179","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An inductor-less 110GHz ring-type frequency divider (RILFD) has been proposed. Body-injection and biasing technique have been adopted to achieve high speed and divide-by-three operation and fine tuning of operation frequency. The RILFD was fabricated by a 1P12M 65nm bulk CMOS process. The core size is 10.8×8.5μm2. The locking range is 9.1%, from 100.8 to 110.4GHz, under varying of body-bias voltage from −0.2V to 0.4V. The RILFD consumes 4.5mW at the supply voltage of 1V excluding an output buffer. The output phase noise is −117.6dBc/Hz at 1MHz offset. This work has been achieved the smallest core size among frequency dividers reported to date operating over 100GHz.
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