D. Worledge, C. Safranski, G. Hu, J. Sun, P. Hashemi, S. Brown, L. Buzi, C. D'Emic, M. Gottwald, O. Gunawan, H. Jung, S. Karimeddiny, J. Kim, P. Trouilloud
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We review the use-case and requirements for Spin-Transfer-Torque MRAM (STT-MRAM) to replace SRAM in last-level-cache. We then describe recent work on double magnetic tunnel junctions and double spin-torque magnetic tunnel junctions to reduce the MRAM switching current. The latter devices open up the possibility of reducing the switching current by a factor of two while maintaining high magnetoresistance, which could enable the use of STT-MRAM in last-level-cache.
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