A New Hardware-Accelerated Scheduler for Soft Real-Time Tasks

This paper presents a coprocessor design that performs task scheduling for soft real-time systems. The proposed solution is based on the Guaranteed Earliest Deadline (GED) algorithm. Thanks to hardware implementation of the scheduler, the scheduler operations are always performed in two clock cycles regardless of the actual number of tasks and the maximum number of tasks in the system. Through synthesis results, two versions of the scheduler were compared: an existing EDF based scheduler and the proposed GED based scheduler. Both schedulers were verified using simplified version of Universal Verification Methodology (UVM) and applying millions of instructions with randomly generated deadline values. The FPGA resource costs have been evaluated by synthesis into Intel FPGA Cyclone V.