{"title":"自适应滞后比较器与opamp阈值水平设置","authors":"N. Ekekwe, R. Etienne-Cummings","doi":"10.1109/MWSCAS.2008.4616751","DOIUrl":null,"url":null,"abstract":"This paper presents the design of an adaptive hysteretic comparator optimized for noisy environment. It features an input rail-to-rail opamp which uses feedback networks to set varying hysteretic thresholds while maintaining a constant hysteretic band for increased noise immunity and stability. The chip which can resolve up to 9 bits consumes a total power of 3.8 mW and takes an active area of 0.021 mm2 in a 2P3M 0.5 mum CMOS process with 20 ns propagation delay.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Adaptive hysteretic comparator with opamp threshold level setting\",\"authors\":\"N. Ekekwe, R. Etienne-Cummings\",\"doi\":\"10.1109/MWSCAS.2008.4616751\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of an adaptive hysteretic comparator optimized for noisy environment. It features an input rail-to-rail opamp which uses feedback networks to set varying hysteretic thresholds while maintaining a constant hysteretic band for increased noise immunity and stability. The chip which can resolve up to 9 bits consumes a total power of 3.8 mW and takes an active area of 0.021 mm2 in a 2P3M 0.5 mum CMOS process with 20 ns propagation delay.\",\"PeriodicalId\":118637,\"journal\":{\"name\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-09-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2008.4616751\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 51st Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2008.4616751","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Adaptive hysteretic comparator with opamp threshold level setting
This paper presents the design of an adaptive hysteretic comparator optimized for noisy environment. It features an input rail-to-rail opamp which uses feedback networks to set varying hysteretic thresholds while maintaining a constant hysteretic band for increased noise immunity and stability. The chip which can resolve up to 9 bits consumes a total power of 3.8 mW and takes an active area of 0.021 mm2 in a 2P3M 0.5 mum CMOS process with 20 ns propagation delay.
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