{"title":"采用RPS门的小型可逆十进制加法器的设计","authors":"R. K. James, K. Jacob, S. Sasi","doi":"10.1109/WICT.2012.6409100","DOIUrl":null,"url":null,"abstract":"This paper presents two universal 4×4 `reversible RPS gates' that can function as a reversible 4-bit Binary to BCD converter with a garbage count of zero. The new `fully or partially reversible RPS gate' gives an optimized design of the offset correction circuit of a reversible Binary Coded Decimal (BCD) adder. The paper proposes reversible implementations of BCD adder using fully reversible RPS gates and using combination of HNC-RPS (fully and partially) gates; and the comparisons are tabulated. The HNG-RPS designs achieve a reduction in garbage outputs and logical complexity compared to the existing reversible BCD adder designs. This can form the basic building block of a high speed decimal `Arithmetic and Logic Unit (ALU)' for a low power reversible `Central Processing Unit (CPU)'.","PeriodicalId":445333,"journal":{"name":"2012 World Congress on Information and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Design of compact reversible decimal adder using RPS gates\",\"authors\":\"R. K. James, K. Jacob, S. Sasi\",\"doi\":\"10.1109/WICT.2012.6409100\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents two universal 4×4 `reversible RPS gates' that can function as a reversible 4-bit Binary to BCD converter with a garbage count of zero. The new `fully or partially reversible RPS gate' gives an optimized design of the offset correction circuit of a reversible Binary Coded Decimal (BCD) adder. The paper proposes reversible implementations of BCD adder using fully reversible RPS gates and using combination of HNC-RPS (fully and partially) gates; and the comparisons are tabulated. The HNG-RPS designs achieve a reduction in garbage outputs and logical complexity compared to the existing reversible BCD adder designs. This can form the basic building block of a high speed decimal `Arithmetic and Logic Unit (ALU)' for a low power reversible `Central Processing Unit (CPU)'.\",\"PeriodicalId\":445333,\"journal\":{\"name\":\"2012 World Congress on Information and Communication Technologies\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 World Congress on Information and Communication Technologies\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WICT.2012.6409100\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 World Congress on Information and Communication Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WICT.2012.6409100","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of compact reversible decimal adder using RPS gates
This paper presents two universal 4×4 `reversible RPS gates' that can function as a reversible 4-bit Binary to BCD converter with a garbage count of zero. The new `fully or partially reversible RPS gate' gives an optimized design of the offset correction circuit of a reversible Binary Coded Decimal (BCD) adder. The paper proposes reversible implementations of BCD adder using fully reversible RPS gates and using combination of HNC-RPS (fully and partially) gates; and the comparisons are tabulated. The HNG-RPS designs achieve a reduction in garbage outputs and logical complexity compared to the existing reversible BCD adder designs. This can form the basic building block of a high speed decimal `Arithmetic and Logic Unit (ALU)' for a low power reversible `Central Processing Unit (CPU)'.