Impedance matching for the reduction of via induced signal reflection in on-chip high speed interconnect lines

Advancements in VLSI technology has made it possible to have more than eight metal layers connecting millions of closely placed devices in a single IC chip. Different interconnect layers run across the chip and the necessary connections across the layers are made through vias. The impedance discontinuity at the junction of the via and the interconnect line creates signal reflections and contributes to the loss of the signal. This paper proposes a method for the reduction of via induced signal reflection in multi layer high speed on-chip interconnect structures. At the junction of the interconnect and the via, impedance mismatch is reduced by the inclusion of an appropriate capacitive load. In this paper, we show the reduction in signal reflection upto a frequency of 9 GHz using the proposed model for the dimensions of 65 nm technology node in the case of two interconnect layers connected through a single via.