FPGA IEEE-754-2008十进制64浮点乘法器

Carlos Minchola, G. Sutter
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引用次数: 11

摘要

本文设计并实现了一个符合现行IEEE-754-2008标准的小数浮点DFP乘法计算硬件模块。提出的设计由独立的阶段:IEEE-754编/解码器、十进制乘法器和舍入。十进制乘法是基于先前设计的BCD乘法器。新颖之处在于为舍入阶段设计了组合和顺序架构。报告和评估时间性能和硬件需求结果。在Virtex 4中,一个十进制的乘法运算可以在66ns内完成。所提供的DFP乘法支持对decimal64格式的操作,并且很容易扩展到decimal128格式。据作者所知,这是第一个在FPGA中介绍IEEE 754-2008乘法器的出版物。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier
This paper describes the design and implementation of a hardware module to calculate the decimal floating-point DFP) multiplication compliant with the current IEEE-754-2008 standard. The design proposed is made up of independent stages: IEEE-754 coder / decoder, decimal multiplier and rounding. The decimal multiplication is based on a previously designed BCD multiplier. The novelty is the design of a combinational and sequential architecture for rounding stage. Time performances and hardware requirements results are reported and evaluated. A decimal64 multiplication is able to be performed in 66 ns in a Virtex 4. The DFP multiplication presented supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To the best of author’s knowledge, this is the first publication to present an IEEE 754-2008 multiplier in FPGA.
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