A high throughput implementation of AES with improved BDD T-box structure

The speed of CBC mode is difficult to develop because of its feedback loop. To improve the speed of CBC mode, a method of removing the XOR gate from the critical path by precomputing T-box which merges S-box and MixColumns operation is proposed in this paper. The implementation of T-box is parallel on the basis of twisted BDD including BDD and 5-32 decoder. We merge the XOR gate into both BDD and the decoder by precalculation so as to eliminate it from the critical path. ASIC implementation proves the effectiveness and we can achieve a throughput of 12.4Gbps using a 0.13μm CMOS standard cell library and this is superior to others compared to previous work.