{"title":"可重构架构的探索:一种经验方法","authors":"W. Ligon, U. Ramachandran","doi":"10.1109/FMPC.1990.89461","DOIUrl":null,"url":null,"abstract":"An approach to designing computer architectures in which architectural features are analyzed for utility and cost with respect to the system software that uses them is applied to reconfigurable architectures. A notation for classifying reconfigurable architectures that covers three major areas of reconfigurable architecture design-processor reconfiguration, control reconfiguration, and connection reconfiguration-is presented. A simulator based on this notation, called the reconfigurable architecture workbench, is described. This has been used to study the effects of processor reconfiguration within the image-processing application domain. Experimental results showing that some types of processor reconfiguration provide significant speedup over parallel architectures without processor reconfiguration are presented. The engineering problems present in implementing processor reconfiguration are explored, and some solutions to these problems are suggested.<<ETX>>","PeriodicalId":193332,"journal":{"name":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","volume":"122 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Exploration of reconfigurable architectures: an empirical approach\",\"authors\":\"W. Ligon, U. Ramachandran\",\"doi\":\"10.1109/FMPC.1990.89461\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An approach to designing computer architectures in which architectural features are analyzed for utility and cost with respect to the system software that uses them is applied to reconfigurable architectures. A notation for classifying reconfigurable architectures that covers three major areas of reconfigurable architecture design-processor reconfiguration, control reconfiguration, and connection reconfiguration-is presented. A simulator based on this notation, called the reconfigurable architecture workbench, is described. This has been used to study the effects of processor reconfiguration within the image-processing application domain. Experimental results showing that some types of processor reconfiguration provide significant speedup over parallel architectures without processor reconfiguration are presented. The engineering problems present in implementing processor reconfiguration are explored, and some solutions to these problems are suggested.<<ETX>>\",\"PeriodicalId\":193332,\"journal\":{\"name\":\"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation\",\"volume\":\"122 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-10-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FMPC.1990.89461\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FMPC.1990.89461","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Exploration of reconfigurable architectures: an empirical approach
An approach to designing computer architectures in which architectural features are analyzed for utility and cost with respect to the system software that uses them is applied to reconfigurable architectures. A notation for classifying reconfigurable architectures that covers three major areas of reconfigurable architecture design-processor reconfiguration, control reconfiguration, and connection reconfiguration-is presented. A simulator based on this notation, called the reconfigurable architecture workbench, is described. This has been used to study the effects of processor reconfiguration within the image-processing application domain. Experimental results showing that some types of processor reconfiguration provide significant speedup over parallel architectures without processor reconfiguration are presented. The engineering problems present in implementing processor reconfiguration are explored, and some solutions to these problems are suggested.<>