基于28nm CMOS的112Gb/s低噪声PAM-4线性光接收机

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI:10.1109/EDSSC.2019.8753978

Yongjun Shi, Dan Li, Shengwei Gao, Yihua Zhang, Li Geng

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引用次数: 1

摘要

提出了一种低噪声、高线性度的28nm CMOS 112Gb/s PAM-4线性光接收机。接收机信号链由一个跨阻放大器(TIA)、一个连续时间线性均衡器(CTLE)、一个可变增益放大器(VGA)和一个输出缓冲器组成。PMOS CML逻辑是基于器件特性使用的。低噪声拓扑结构和新颖的增益控制技术共同实现了最先进的性能。接收机的输入参考噪声电流为2.72 $\mu$ Arms，跨阻增益为71dB $\Omega$，带宽为37 GHz。它能够提供18.5dB动态范围，以支持1.8mApp的最大输入过载电流。口琴总失真(THD)低于5% under 660mVpp output swing. This receiver consumes 96.8mW from 1.5V supply.

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A 112Gb/s Low-Noise PAM-4 Linear Optical Receiver in 28nm CMOS

A 112Gb/s PAM-4 linear optical receiver with low noise, high linearity in 28nm CMOS is presented. The receiver signal chain consists of a transimpedance amplifier (TIA), a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. PMOS CML logic is used based on the device characteristics. The low-noise topology and novel gain control techniques together enable state-of-the-art performance. The receiver achieves 2.72$\mu$ Arms input-referred noise current, 71dB $\Omega$ transimpedance gain and 37 GHz bandwidth. It is able to provide 18.5dB dynamic range to support maximum input overload current of 1.8mApp. The total harmonica distortion (THD) is below 5% under 660mVpp output swing. This receiver consumes 96.8mW from 1.5V supply.

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来源期刊

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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