Sonar: Writing Testbenches through Python

Design verification is an important though time-consumingaspect of hardware design. A good testbench should supportperforming functional coverage of a design by making iteasy to implement tests and determine which tests are beingperformed. However, for complex designs, creating and main-taining effective testbenches can take increasing amounts oftime away from actual design. A further complication is theremay be two development flows: conventional hardware writtenin a hardware description language (HDL) such as Verilog orVHDL and high-level synthesis (HLS). In the HLS approach, the hardware is specified in a higher-level language (HLL) and then converted to an HDL through HLS tools. In thisflow, testbenches for the design are written in the same HLLand cosimulation is used to verify the generated HDL. Due totool restrictions, cosimulation may not always work. In VivadoHLS [1] for example, the design must contain control signalsto define when to start and stop the module or the initiationinterval for new data must be one cycle. Without cosimulation, the user must write an HDL testbench manually in additionto a testbench in the HLL for preliminary verification. Tosimplify writing testbenches, we present Sonar: an open-sourcePython library to write cross-language testbenches. From acommon source script, Sonar can generate testbenches writtenin SystemVerilog (SV) and C++. These files can then beimported into standard simulation tools such as ModelSim[2] or Vivado HLS and run. The use of Python makes iteasy to extend Sonar with higher layers of abstraction fortestbenches and integrate it with other software platforms.Sonar is available at https://github.com/UofT-HPRC/sonar.