数字计算机和容错系统故障行为的表征

[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track Pub Date : 1989-01-03 DOI:10.1109/HICSS.1989.47155

S. Bavuso, P. Miner

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引用次数: 0

摘要

讨论了数字容错系统中潜在故障特征的研究。一系列的研究导致了一个实用的高速门级逻辑模拟器的发展。讨论了采用可故障软件对高速模拟器进行验证，并对MIS-STD-1750A原型处理器进行了硬件仿真。

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Characterization of the faulted behavior of digital computers and fault tolerant systems

Research that is being conducted to characterize the latent fault in digital fault-tolerant systems is addressed. A series of investigations that have led to the development of a practical high-speed gate-level logic simulator is described. The validation of the high-speed simulator, using faultable software, and hardware simulations of a prototype MIS-STD-1750A processor are discussed.<>

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[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track

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