{"title":"先进的兼容N-MOS, CMOS和双极晶体管的LSI工艺","authors":"B. Hoefflinger, J. Schneider, G. Zimmer","doi":"10.1109/IEDM.1977.189225","DOIUrl":null,"url":null,"abstract":"An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Advanced compatible LSI process for N-MOS, CMOS and bipolar transistors\",\"authors\":\"B. Hoefflinger, J. Schneider, G. Zimmer\",\"doi\":\"10.1109/IEDM.1977.189225\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.\",\"PeriodicalId\":218912,\"journal\":{\"name\":\"1977 International Electron Devices Meeting\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1977 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1977.189225\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1977 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1977.189225","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Advanced compatible LSI process for N-MOS, CMOS and bipolar transistors
An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.
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