A flexible dataflow CNN accelerator on FPGA

With the increasing diversity of neural networks, accelerators supporting multiple dataflows are more efficient than those only supporting a specific dataflow. However, due to different storage structures and transmission patterns in different dataflows, deploying an accelerator with multiple heterogeneous cores on FPGA that lacks resources is challenging. In this paper, we present an instruction-based CNN accelerator supporting flexible dataflow. Towards reducing the resource occupation of FPGA, we propose a novel architecture with a delicate data path reusing the storage module and the computing module. In addition, a special instruction mechanism is designed to control the data transmission. As a case study, we implement a prototype and test it on ResNet18 and MobileNetv1. Results show, compared to the multi-core accelerator that supports the flexible dataflow, we achieve 1.3-2.7x speedup.