低功耗技术映射中的节点归一化与分解

Proceedings of 1997 International Symposium on Low Power Electronics and Design Pub Date : 1997-08-01 DOI:10.1145/263272.263351

W. Nöth, Reiner Kolla

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引用次数: 14

摘要

在CMOS技术中，电路节点的分解可以显著降低电路的功耗。提出了一种提取给定网表中最大节点的归一化算法。然后，我们对已知的节点分解算法进行了研究，提出了一种新的节点分解算法，该算法在中等节点大小的情况下是可证明的最优和易于处理的。对于精确(ROBDD)和不相关信号概率，标准基准电路上的总体开关活动的减少显示。

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Node normalization and decomposition in low power technology mapping

In CMOS technology the decomposition of the nodes of a circuit can significantly reduce the circuit power dissipation. We present a normalization algorithm which extracts the largest nodes of the given netlist. Then we examine a known node decomposition algorithm and propose a new one which is provable optimal and tractable for moderate node sizes. Reduction of the overall switching activity on standard benchmark circuits is shown for exact (ROBDD) and uncorrelated signal probabilities.

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Proceedings of 1997 International Symposium on Low Power Electronics and Design

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