{"title":"5G相控阵毫米波威尔金森功率合成器的分析、设计与建模","authors":"Jinhua Chen, Peng Miao, Dixian Zhao","doi":"10.1109/IEEE-IWS.2019.8803964","DOIUrl":null,"url":null,"abstract":"A Wilkinson power combiner performed in shielded coplanar waveguide is presented in this paper. A lumped circuit model has been proposed for the design and optimization of this work. Fabricated in 65-nm CMOS technology, the Wilkinson power combiner occupies a core chip area of 266 × 382 μm2. The measured insertion loss is 0.92-1.33 dB at 20-40 GHz. The input return loss is better than 15.5 dB and the output return loss is better than 25 dB from 20 to 40 GHz. The port-to-port isolation is better than 14.5 dB from 20 to 40 GHz.","PeriodicalId":306297,"journal":{"name":"2019 IEEE MTT-S International Wireless Symposium (IWS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Analysis, Design and Modeling of Millimeter-Wave Wilkinson Power Combiner for 5G Phased Array\",\"authors\":\"Jinhua Chen, Peng Miao, Dixian Zhao\",\"doi\":\"10.1109/IEEE-IWS.2019.8803964\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Wilkinson power combiner performed in shielded coplanar waveguide is presented in this paper. A lumped circuit model has been proposed for the design and optimization of this work. Fabricated in 65-nm CMOS technology, the Wilkinson power combiner occupies a core chip area of 266 × 382 μm2. The measured insertion loss is 0.92-1.33 dB at 20-40 GHz. The input return loss is better than 15.5 dB and the output return loss is better than 25 dB from 20 to 40 GHz. The port-to-port isolation is better than 14.5 dB from 20 to 40 GHz.\",\"PeriodicalId\":306297,\"journal\":{\"name\":\"2019 IEEE MTT-S International Wireless Symposium (IWS)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE MTT-S International Wireless Symposium (IWS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEEE-IWS.2019.8803964\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE MTT-S International Wireless Symposium (IWS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEE-IWS.2019.8803964","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis, Design and Modeling of Millimeter-Wave Wilkinson Power Combiner for 5G Phased Array
A Wilkinson power combiner performed in shielded coplanar waveguide is presented in this paper. A lumped circuit model has been proposed for the design and optimization of this work. Fabricated in 65-nm CMOS technology, the Wilkinson power combiner occupies a core chip area of 266 × 382 μm2. The measured insertion loss is 0.92-1.33 dB at 20-40 GHz. The input return loss is better than 15.5 dB and the output return loss is better than 25 dB from 20 to 40 GHz. The port-to-port isolation is better than 14.5 dB from 20 to 40 GHz.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
