{"title":"在键合和蚀刻的InP-on-Si上生长和制备InGaAs/InAlAs hemt","authors":"A. Fathimulla, J. Abrahams, H. Hier, T. Loughran","doi":"10.1109/ICIPRM.1990.202986","DOIUrl":null,"url":null,"abstract":"InGaAs/InAlAs HEMTs fabricated on bonded-and-etched-back InP-on-Si substrates are reported. The process involves depositing SiO/sub 2/ on both the Si and InP substrates. The wafers are then contacted and bonded in a furnace at low temperature. Defects in the bond can be minimized by bonding in a particle-free environment. After bonding to a Si substrate, the InP wafer is thinned to <10 mu m and a strain-relief grid is etched through the InP to the SiO/sub 2/ layer. For fabrication of the HEMT, a standard processing sequence of mesa isolation, ohmic-contacts formation, gate-metal deposition and overlay was used. A maximum transconductance of 180 mS/mm was measured for a 1.2- mu m-gate-length device.<<ETX>>","PeriodicalId":138960,"journal":{"name":"International Conference on Indium Phosphide and Related Materials","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Growth and fabrication of InGaAs/InAlAs HEMTs on bonded-and-etch-back InP-on-Si\",\"authors\":\"A. Fathimulla, J. Abrahams, H. Hier, T. Loughran\",\"doi\":\"10.1109/ICIPRM.1990.202986\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"InGaAs/InAlAs HEMTs fabricated on bonded-and-etched-back InP-on-Si substrates are reported. The process involves depositing SiO/sub 2/ on both the Si and InP substrates. The wafers are then contacted and bonded in a furnace at low temperature. Defects in the bond can be minimized by bonding in a particle-free environment. After bonding to a Si substrate, the InP wafer is thinned to <10 mu m and a strain-relief grid is etched through the InP to the SiO/sub 2/ layer. For fabrication of the HEMT, a standard processing sequence of mesa isolation, ohmic-contacts formation, gate-metal deposition and overlay was used. A maximum transconductance of 180 mS/mm was measured for a 1.2- mu m-gate-length device.<<ETX>>\",\"PeriodicalId\":138960,\"journal\":{\"name\":\"International Conference on Indium Phosphide and Related Materials\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Indium Phosphide and Related Materials\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIPRM.1990.202986\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Indium Phosphide and Related Materials","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIPRM.1990.202986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Growth and fabrication of InGaAs/InAlAs HEMTs on bonded-and-etch-back InP-on-Si
InGaAs/InAlAs HEMTs fabricated on bonded-and-etched-back InP-on-Si substrates are reported. The process involves depositing SiO/sub 2/ on both the Si and InP substrates. The wafers are then contacted and bonded in a furnace at low temperature. Defects in the bond can be minimized by bonding in a particle-free environment. After bonding to a Si substrate, the InP wafer is thinned to <10 mu m and a strain-relief grid is etched through the InP to the SiO/sub 2/ layer. For fabrication of the HEMT, a standard processing sequence of mesa isolation, ohmic-contacts formation, gate-metal deposition and overlay was used. A maximum transconductance of 180 mS/mm was measured for a 1.2- mu m-gate-length device.<>
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