{"title":"用于15位25 kHz音频ΣΔ调制器的7.3 μW抽取滤波器","authors":"Mehmet Ince, Feyyaz Melih Akcakaya, G. Dundar","doi":"10.1109/FTFC.2014.6828601","DOIUrl":null,"url":null,"abstract":"This paper presents a low power decimation filter designed for oversampling ΣΔ Analog to Digital Converters (ADC). The Decimation filter consists of three stages; namely, CIC filter, Half-Band filter, and FIR filter. In order to reduce power, Canonical Signed Digit (CSD) representation, multiplierless filter architecture, polyphase structure, and multistage CIC structure are utilized. In addition, Finite Impulse Response (FIR) is designed using the GAM algorithm. The proposed filter is synthesized with CMOS 0.18 μm technology. It consumes 7.25 μW for 15 bit Audio ΣΔ Modulator with sampling frequency of 1.6 MHz and 25 kHz bandwidth.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 7.3 μW decimation filter for 15 bit 25 kHz audio ΣΔ modulator\",\"authors\":\"Mehmet Ince, Feyyaz Melih Akcakaya, G. Dundar\",\"doi\":\"10.1109/FTFC.2014.6828601\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low power decimation filter designed for oversampling ΣΔ Analog to Digital Converters (ADC). The Decimation filter consists of three stages; namely, CIC filter, Half-Band filter, and FIR filter. In order to reduce power, Canonical Signed Digit (CSD) representation, multiplierless filter architecture, polyphase structure, and multistage CIC structure are utilized. In addition, Finite Impulse Response (FIR) is designed using the GAM algorithm. The proposed filter is synthesized with CMOS 0.18 μm technology. It consumes 7.25 μW for 15 bit Audio ΣΔ Modulator with sampling frequency of 1.6 MHz and 25 kHz bandwidth.\",\"PeriodicalId\":138166,\"journal\":{\"name\":\"2014 IEEE Faible Tension Faible Consommation\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Faible Tension Faible Consommation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FTFC.2014.6828601\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Faible Tension Faible Consommation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FTFC.2014.6828601","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 7.3 μW decimation filter for 15 bit 25 kHz audio ΣΔ modulator
This paper presents a low power decimation filter designed for oversampling ΣΔ Analog to Digital Converters (ADC). The Decimation filter consists of three stages; namely, CIC filter, Half-Band filter, and FIR filter. In order to reduce power, Canonical Signed Digit (CSD) representation, multiplierless filter architecture, polyphase structure, and multistage CIC structure are utilized. In addition, Finite Impulse Response (FIR) is designed using the GAM algorithm. The proposed filter is synthesized with CMOS 0.18 μm technology. It consumes 7.25 μW for 15 bit Audio ΣΔ Modulator with sampling frequency of 1.6 MHz and 25 kHz bandwidth.
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