Design and Performance Analysis of Improved FIR Filter using UltraScale FPGA

It is discussed in many studies and demonstrated in the many researches that based on certain applications, analog design of filter has several issues including complex design, re-use Limitations, and accuracy of generating the output at various frequencies. Therefore, instead of analog filter design the digital design of the filter is preferred for both Finite and Infinite Impulse Response Filter. This paper demonstrates the design of the digital FIR filter designed is demonstrated using ultrascale Field Programming Gate Array. The filter is designed using Coefficient multiplier via Canonic Signed Digit – CSD Technique. The optimized design of digital filter is carried out via real-time implementation is performed using Ultra Scale FPGA. The filter is designed and tested with ordinary filter at 10 MHz and 10 GHz frequencies. The performance analysis of the system is illustrated using the response rate at the bit stream of 16 bit. In the results, it is demonstrated that for 10 MHz frequency design FIR filter in FPGA the 30% faster response filter is achieved at for 10 GHz, the 15% faster response is achieved at the IO Standard of LVCOMS. The proposed Improved Finite Impulse Response Filter Design using Ultra Scale FPGA helps in increasing design performance to increase the speed of overall response of FIR filter that is lacking in ordinary Filters.