PERL-a registerless architecture

Reducing processor memory speed gap is one of the major challenges computer architects face today. Efficient use of CPU registers reduces the number of memory accesses. However, registers do incur extra overhead of load/store, register allocation and saving of register context across procedure calls. Caches however do not have any such overheads and cache technology has matured to the extent that today the access time of on-chip cache is almost equal to that of registers. This motivates one to explore alternate ways to do away with the overheads of registers. We propose a registerless, memory to memory architecture of a processor. We call this architecture Performance Enhanced Registerless (PERL) processor. All instructions in this processor operate directly on memory operands thus eliminating the load/store and other overheads of registers. The performance of this machine is studied by simulations and results are reported in the paper.