{"title":"光纤计算机互连的OEIC封装","authors":"K. Jackson","doi":"10.1364/odp.1993.wc.1","DOIUrl":null,"url":null,"abstract":"The challenges facing optoelectronic packaging for fiber-optic computer interconnects will be discussed with emphasis on parallel array implementations.","PeriodicalId":296845,"journal":{"name":"Optical Design for Photonics","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"OEIC Packaging for Fiber Optic Computer Interconnects\",\"authors\":\"K. Jackson\",\"doi\":\"10.1364/odp.1993.wc.1\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The challenges facing optoelectronic packaging for fiber-optic computer interconnects will be discussed with emphasis on parallel array implementations.\",\"PeriodicalId\":296845,\"journal\":{\"name\":\"Optical Design for Photonics\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Optical Design for Photonics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1364/odp.1993.wc.1\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Optical Design for Photonics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1364/odp.1993.wc.1","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
OEIC Packaging for Fiber Optic Computer Interconnects
The challenges facing optoelectronic packaging for fiber-optic computer interconnects will be discussed with emphasis on parallel array implementations.