{"title":"存在频率选择iq不平衡和CFO的Ofdm接收机设计","authors":"Muhammad Asim, M. Ghogho, D. McLernon","doi":"10.5281/ZENODO.43728","DOIUrl":null,"url":null,"abstract":"Direct conversion receivers (DCR) are the preferred choice for the RF front-end in modern communication devices. These devices are simple and cheap to implement but for the case of sensitive multicarrier systems these devices may not maintain the required level of performance as regards image rejection (IR), carrier frequency offset (CFO) and direct current offset. In the presence of this non-ideal behaviour it is not possible to achieve a high signal to interferer ratio (SIR). This situation necessitates the use of digital signal processing (DSP) schemes to efficiently mitigate these effects and also to relax the stringent requirements on receiver design. In this paper we study the design of a receiver architecture which can jointly estimate the channel impulse response (CIR), IQ imbalance and CFO using long training sequences (LTS) which are already a part of WLAN standards. The proposed schemes provide an excellent performance/complexity tradeoff.","PeriodicalId":400766,"journal":{"name":"21st European Signal Processing Conference (EUSIPCO 2013)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Ofdm receiver design in the presence of frequency selective iq imbalance and CFO\",\"authors\":\"Muhammad Asim, M. Ghogho, D. McLernon\",\"doi\":\"10.5281/ZENODO.43728\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Direct conversion receivers (DCR) are the preferred choice for the RF front-end in modern communication devices. These devices are simple and cheap to implement but for the case of sensitive multicarrier systems these devices may not maintain the required level of performance as regards image rejection (IR), carrier frequency offset (CFO) and direct current offset. In the presence of this non-ideal behaviour it is not possible to achieve a high signal to interferer ratio (SIR). This situation necessitates the use of digital signal processing (DSP) schemes to efficiently mitigate these effects and also to relax the stringent requirements on receiver design. In this paper we study the design of a receiver architecture which can jointly estimate the channel impulse response (CIR), IQ imbalance and CFO using long training sequences (LTS) which are already a part of WLAN standards. The proposed schemes provide an excellent performance/complexity tradeoff.\",\"PeriodicalId\":400766,\"journal\":{\"name\":\"21st European Signal Processing Conference (EUSIPCO 2013)\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-09-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"21st European Signal Processing Conference (EUSIPCO 2013)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.5281/ZENODO.43728\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st European Signal Processing Conference (EUSIPCO 2013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.5281/ZENODO.43728","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Ofdm receiver design in the presence of frequency selective iq imbalance and CFO
Direct conversion receivers (DCR) are the preferred choice for the RF front-end in modern communication devices. These devices are simple and cheap to implement but for the case of sensitive multicarrier systems these devices may not maintain the required level of performance as regards image rejection (IR), carrier frequency offset (CFO) and direct current offset. In the presence of this non-ideal behaviour it is not possible to achieve a high signal to interferer ratio (SIR). This situation necessitates the use of digital signal processing (DSP) schemes to efficiently mitigate these effects and also to relax the stringent requirements on receiver design. In this paper we study the design of a receiver architecture which can jointly estimate the channel impulse response (CIR), IQ imbalance and CFO using long training sequences (LTS) which are already a part of WLAN standards. The proposed schemes provide an excellent performance/complexity tradeoff.