An Iterative Technique for Runtime Efficient Hardware-Software Partitioning

The increasing popularity of FPGA-based devices for applications of different size and complexity calls for runtime efficient hardware-software partitioning techniques with high levels of accuracy. However, the prohibitively large design space during partitioning makes this task a challenging one, leading to restrictions on the design space at the cost of accuracy. In this work, we propose an iterative technique for runtime efficient hardware-software partitioning based on a divide and conquer algorithm. The proposed techniques have been evaluated using applications from the CHstone benchmark suite with accuracy of 94% and 99% compared to implementation and an exhaustive technique respectively, with significantly low runtimes.