36位宽Fifo深度,面向总线的应用

M. Muegge, D. Chenoweth
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引用次数: 0

摘要

专用存储器,如FIFO设备,其高性能来源于其架构和底层技术。FIFO设备对更高速度的需求导致了越来越快的设备的引入,其访问时间低至10ns,例如QS7204-10。然而,传统的FIFO接口,即使在10ns访问时间级别,也无法满足当今领先的CPU性能要求。时钟接口允许更好地利用内存带宽,并且可以在现实世界的系统环境中提供66 MHz甚至更高的数据速率。高速,36位宽FIFO器件,封装在小间距TQFP封装,实现高性能,高密度的系统设计。本文重点介绍了FIFO器件的三个方面:速度、字深和附加的增值功能,以展示这些增强功能如何提高系统性能和板效率。>
本文章由计算机程序翻译,如有差异,请以英文原文为准。
36 Bit Wide Fifo For Deep, Bus Oriented Applications
Speciality memories, such as FIFO devices, derive their high performance from their architecture as well as their underlying technology. The need for higher speed in FIFO devices has resulted in the introduction of faster and faster devices, with access times as low as 10 ns, such as the QS7204-10. Nevertheless, traditional FIFO interfaces, even at the 10 ns access time level, fall short of meeting today's leading edge CPU performance requirements. Clocked interfaces allow better utilization of the memory bandwidth and can provide data rates of 66 MHz and beyond in real world system environments. High speed, 36 bit wide FIFO devices, packaged in the fine pitch TQFP package, enable high performance, high density system designs. This paper focuses on three aspects of FIFO devices: speed, word depth, and additional value added features to show how these enhancements can boost system performance and board efficiency. >
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