jfet输入，高速比较器标准单元设计在一系列新的模拟阵列上

Proceedings of the 1988 Bipolar Circuits and Technology Meeting, Pub Date : 1988-09-12 DOI:10.1109/BIPOL.1988.51050

M. Metcalf

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引用次数: 1

摘要

在半定制集成电路上设计了一种性能远远超过现有技术的单片JFET输入比较器。使用模拟阵列在设计工作，制造时间和布局通用性方面提供了好处，而不会牺牲卓越的性能。

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JFET-input, high speed comparator standard cell designed on a new series of analog arrays

A monolithic JFET input comparator with performance that far exceeds any prior art has been designed on a semicustom IC. The use of the analog array provided benefits in design effort, manufacturing time and layout versatility without sacrificing excellence performance.<>

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Proceedings of the 1988 Bipolar Circuits and Technology Meeting,

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