一种基于倍频的相控阵本相移技术

Y. Soliman, R. Mason
{"title":"一种基于倍频的相控阵本相移技术","authors":"Y. Soliman, R. Mason","doi":"10.1109/RWS.2010.5434257","DOIUrl":null,"url":null,"abstract":"A frequency multiplication based LO phase shifting technique is presented for use in phased-array front end architectures operating in the ISM band at 24GHz. The presented architecture employs a two-stage phase shifter, a high-speed comparator and a Q-enhanced tuned amplifier to synthesize 18GHz tones from a 2GHz reference. The synthesized tones are used to injection lock 18GHz LC-oscillators in close proximity to the RF/mm-w front-ends in a phased-array system. A digital means for phase shift calibration is discussed. Implemented in IBM's 120 nm CMOS technology, the proposed architecture consumes 14.2mW from a 1.2V supply. The oscillator core consumes 3.7mW. The maximum phase shift errors at 18GHz is 5° and 0.79° before and after calibration, respectively.","PeriodicalId":334671,"journal":{"name":"2010 IEEE Radio and Wireless Symposium (RWS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A frequency multiplication based LO phase shifting technique for phased-array architectures\",\"authors\":\"Y. Soliman, R. Mason\",\"doi\":\"10.1109/RWS.2010.5434257\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A frequency multiplication based LO phase shifting technique is presented for use in phased-array front end architectures operating in the ISM band at 24GHz. The presented architecture employs a two-stage phase shifter, a high-speed comparator and a Q-enhanced tuned amplifier to synthesize 18GHz tones from a 2GHz reference. The synthesized tones are used to injection lock 18GHz LC-oscillators in close proximity to the RF/mm-w front-ends in a phased-array system. A digital means for phase shift calibration is discussed. Implemented in IBM's 120 nm CMOS technology, the proposed architecture consumes 14.2mW from a 1.2V supply. The oscillator core consumes 3.7mW. The maximum phase shift errors at 18GHz is 5° and 0.79° before and after calibration, respectively.\",\"PeriodicalId\":334671,\"journal\":{\"name\":\"2010 IEEE Radio and Wireless Symposium (RWS)\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-01-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE Radio and Wireless Symposium (RWS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RWS.2010.5434257\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Radio and Wireless Symposium (RWS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2010.5434257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

提出了一种基于倍频的本相移技术,用于在24GHz ISM频段工作的相控阵前端架构。所提出的架构采用两级移相器、高速比较器和q增强调谐放大器,从2GHz基准合成18GHz音调。合成的音调用于注入锁定相控阵系统中靠近RF/mm-w前端的18GHz lc振荡器。讨论了一种数字相移校准方法。该架构采用IBM的120纳米CMOS技术,功耗为14.2mW,电源电压为1.2V。振荡器芯消耗3.7mW。在18GHz时,校准前后的最大相移误差分别为5°和0.79°。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A frequency multiplication based LO phase shifting technique for phased-array architectures
A frequency multiplication based LO phase shifting technique is presented for use in phased-array front end architectures operating in the ISM band at 24GHz. The presented architecture employs a two-stage phase shifter, a high-speed comparator and a Q-enhanced tuned amplifier to synthesize 18GHz tones from a 2GHz reference. The synthesized tones are used to injection lock 18GHz LC-oscillators in close proximity to the RF/mm-w front-ends in a phased-array system. A digital means for phase shift calibration is discussed. Implemented in IBM's 120 nm CMOS technology, the proposed architecture consumes 14.2mW from a 1.2V supply. The oscillator core consumes 3.7mW. The maximum phase shift errors at 18GHz is 5° and 0.79° before and after calibration, respectively.
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