{"title":"用于容错系统的高速通信器","authors":"J. Prizant","doi":"10.1109/DASC.1998.741517","DOIUrl":null,"url":null,"abstract":"A layered architecture for a communicator was presented which allows four COTS processor boards, each in a standard backplane such as VMEbus or CompactPCI, to be networked together to produce a quad-redundant fault tolerant computer. The communicator features a high-bandwidth data exchange making data reliably congruent across the four channels.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High speed communicator for fault tolerant systems\",\"authors\":\"J. Prizant\",\"doi\":\"10.1109/DASC.1998.741517\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A layered architecture for a communicator was presented which allows four COTS processor boards, each in a standard backplane such as VMEbus or CompactPCI, to be networked together to produce a quad-redundant fault tolerant computer. The communicator features a high-bandwidth data exchange making data reliably congruent across the four channels.\",\"PeriodicalId\":335827,\"journal\":{\"name\":\"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DASC.1998.741517\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DASC.1998.741517","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High speed communicator for fault tolerant systems
A layered architecture for a communicator was presented which allows four COTS processor boards, each in a standard backplane such as VMEbus or CompactPCI, to be networked together to produce a quad-redundant fault tolerant computer. The communicator features a high-bandwidth data exchange making data reliably congruent across the four channels.