Hardware implementation of MIMO OFDMA test bed and its application towards channel characterization on indoor LAB test environment

In this article, we present a hardware architecture of MIMO-OFDMA test bed. The testbed is designed in Field Programmable Gate Array (FPGA) in order to provide maximum flexibility in implementation. A modularized design approach is adopted which enables easy implementation, Integration, and testing algorithms of various physical layer modules of OFDMA. The entire physical layer design is successfully implemented in a single Virtex-4 FPGA processing core. The designed testbed architecture features up to 2×2 MIMO implementation with different MIMO modes and Frequency Domain Link Adaptation (FDLA). However, It is also discussed that the design can support up to 4×4 MIMO implementation depending on the choice of PHY design parameters such as FFT Size and FPGA processing frequency. The design is shown to be flexible and reconfigurable to work with different configurations using minimal PHY layer design alterations. The real-time over the air performance results are obtained using over-the-air transmission and reception of data traffic through the testbed. Finally, over-the-air performance results of the testbed are calibrated with the simulated performance over the SUI-3 channel. The implementation is performed on Wireless Open-Access Research Platform (WARP). LTE Release-10 parameters are adopted for designing the testbed.