Digital polar transmitter using a watt-class current-mode class-D CMOS power amplifier

A digital polar transmitter with a watt-class CMOS power amplifier is demonstrated, implemented with a 0.15um RF CMOS process. Current-mode class-D configuration and stacked FETs are used to obtain high efficiency and high breakdown voltage in the output stage, which was measured to have 31 dBm output power with 51% drain efficiency under single tone testing. The output stage is fed by a buck converter employing digital pulse width modulation with 47 MHz pulse rate synchronized with a 3 GHz clock. Digital compensation techniques were developed to maintain linearity. WCDMA HPSK modulation was demonstrated using a pulse pattern generator-based measurement bench. Overall efficiency of 26.5 % efficiency was achieved while maintaining ACLRs within 3GPP specifications at 24 dBm average output power.