{"title":"用于10nm技术的高性能低泄漏口袋SixGe1-x无结单栅隧道场效应管","authors":"S. Tripathi, S. K. Sinha, G. Patel, S. Awasthi","doi":"10.1109/EDKCON.2018.8770480","DOIUrl":null,"url":null,"abstract":"This paper presents a low leakage pocket Six-Ge1-x, junction-less tunnel FET suitable under low voltage region. Junction-less single-gate TFET expolits the steep subthreshold characteristics of tunnel FET as well as the high on current due to junction-less behaviour. Pocket region(5nm) of narrow band gap material Six-Ge1-x, decreases tunneling distance and improves the $\\mathrm{I}_{\\mathrm{o}\\mathrm{n}}/\\mathrm{I}_{\\mathrm{o}\\mathrm{f}\\mathrm{f}}$ ratio. The proposed pocket Junction-less TFET has been designed on 2D/3D Visual TCAD device simulator for 10nm technology to optimize subthreshold parameters such as subthreshold slope, drain induced barrier lowering and leakage current. Such low leakage, low power pocket Junction-less SGTFET is suitable for analog and digital applications.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"High Performance Low Leakage Pocket SixGe1-x Junction-Less Single-Gate Tunnel FET for 10 nm Technology\",\"authors\":\"S. Tripathi, S. K. Sinha, G. Patel, S. Awasthi\",\"doi\":\"10.1109/EDKCON.2018.8770480\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low leakage pocket Six-Ge1-x, junction-less tunnel FET suitable under low voltage region. Junction-less single-gate TFET expolits the steep subthreshold characteristics of tunnel FET as well as the high on current due to junction-less behaviour. Pocket region(5nm) of narrow band gap material Six-Ge1-x, decreases tunneling distance and improves the $\\\\mathrm{I}_{\\\\mathrm{o}\\\\mathrm{n}}/\\\\mathrm{I}_{\\\\mathrm{o}\\\\mathrm{f}\\\\mathrm{f}}$ ratio. The proposed pocket Junction-less TFET has been designed on 2D/3D Visual TCAD device simulator for 10nm technology to optimize subthreshold parameters such as subthreshold slope, drain induced barrier lowering and leakage current. Such low leakage, low power pocket Junction-less SGTFET is suitable for analog and digital applications.\",\"PeriodicalId\":344143,\"journal\":{\"name\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"volume\":\"169 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDKCON.2018.8770480\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDKCON.2018.8770480","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Performance Low Leakage Pocket SixGe1-x Junction-Less Single-Gate Tunnel FET for 10 nm Technology
This paper presents a low leakage pocket Six-Ge1-x, junction-less tunnel FET suitable under low voltage region. Junction-less single-gate TFET expolits the steep subthreshold characteristics of tunnel FET as well as the high on current due to junction-less behaviour. Pocket region(5nm) of narrow band gap material Six-Ge1-x, decreases tunneling distance and improves the $\mathrm{I}_{\mathrm{o}\mathrm{n}}/\mathrm{I}_{\mathrm{o}\mathrm{f}\mathrm{f}}$ ratio. The proposed pocket Junction-less TFET has been designed on 2D/3D Visual TCAD device simulator for 10nm technology to optimize subthreshold parameters such as subthreshold slope, drain induced barrier lowering and leakage current. Such low leakage, low power pocket Junction-less SGTFET is suitable for analog and digital applications.