Design of adder and binary multiplier in QCA using coplanar technique

CMOS is working on the moore's law, but according to moore's law the number of transistor on a single chip will be double after every 18 months, so CMOS technology is going to reach its physical scaling limit by next few years. Several emerging technologies are there to replace the CMOS technology. QCA (Quantum-dot Cellular Automata) is one of the dominating technology having a very high speed, high density and very low power consumption. A Unique methodology for computation and communication are offered by QCA, namely “processing in wire” and “memory-in-motion”. In digital system the necessity of adder and multiplier circuitry is very common. It may be using either integer or the floating point number for its application, the operands should be executed at very high speed. In this paper we are using the fixed point number instead of floating point number. The multiplier is the elementary component of arithmetic logic unit; thus it has a great impact on the performance of central processing unit (CPU). we have presented ripple carry adder (RCA) using full adder(FA), and the 4-bit by 4-bit binary multiplier.