采用超前进位的动态十进制加法器电路设计

2006 IEEE Design and Diagnostics of Electronic Circuits and systems Pub Date : 2006-04-18 DOI:10.1109/DDECS.2006.1649627

Y. You, Yong-Dae Kim, J. Choi

{"title":"采用超前进位的动态十进制加法器电路设计","authors":"Y. You, Yong-Dae Kim, J. Choi","doi":"10.1109/DDECS.2006.1649627","DOIUrl":null,"url":null,"abstract":"This paper presents a carry look ahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 mum CMOS technology yields the worst case delay of 622 ns","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Dynamic Decimal Adder Circuit Design by using the Carry Lookahead\",\"authors\":\"Y. You, Yong-Dae Kim, J. Choi\",\"doi\":\"10.1109/DDECS.2006.1649627\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a carry look ahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 mum CMOS technology yields the worst case delay of 622 ns\",\"PeriodicalId\":158707,\"journal\":{\"name\":\"2006 IEEE Design and Diagnostics of Electronic Circuits and systems\",\"volume\":\"122 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Design and Diagnostics of Electronic Circuits and systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2006.1649627\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2006.1649627","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

本文提出了一种基于动态电路的超前进位(CLA)电路设计，以减少BCD编码十进制数的延迟为目标。对所提出的动态十进制加法器的性能进行了分析，证明了其速度的提高。采用0.25 μ m CMOS技术对所提出的十进制加法电路进行时序仿真，其最坏情况延迟为622 ns

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Dynamic Decimal Adder Circuit Design by using the Carry Lookahead

This paper presents a carry look ahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 mum CMOS technology yields the worst case delay of 622 ns

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2006 IEEE Design and Diagnostics of Electronic Circuits and systems

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