Novel VLSI multi-bit coded multiplier and multiplier-accumulator architectures for DSP applications

In this paper we propose two new algorithms for (i) concurrent computation of odd digit partial products (PPs) and the inner-product-step and (ii) minimization of sign extension bits and map them onto a novel concurrent VLSI architecture based on carry-save 4:2/7:3 compressors for designing efficient multi-bit coded multipliers and multiplier-accumulator (MAC) cells. The use of the proposed architecture results in the total elimination of the separate adder modules normally required for performing the odd-digit PP computation and the inner-product step. Besides, there is a reduction in the input data path complexity of the multiplexers from O(2/sup k-1/) in the conventional schemes to O(k). As a result, approximate reductions ranging from 15% to 40% in the computation time and area are achieved along with reduced number of interconnections making the proposed schemes highly attractive for VLSI implementation for performing multi-bit recoding even for k>6, k being the recoding size. This important feature makes the proposed architecture attractive also to be used in low-power and pipelined DSP applications.