一个0.55V 100MHz ADPLL， ΔΣ LDO和弛豫DCO, 65nm CMOS

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Pub Date : 2015-08-01 DOI:10.1109/RFIT.2015.7377930

Yudong Zhang, W. Rhee, Zhihua Wang, Taeik Kim, Hojin Park

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引用次数: 2

摘要

在65nm CMOS中实现了一个0.55V 100MHz ldo嵌入式ADPLL。设计了一种具有可变阈值逆变器和数字校准电路的数字控制弛豫振荡器(DCRXO)，用于超低电源电压下的鲁棒启动。ΔΣ调制伪数字LDO为DCRXO提供pvt不敏感的抖动内部电压。包含LDO的100MHz ADPLL从0.55V电源消耗67μW，在1MHz偏移频率下实现-82.9dBc/Hz的相位噪声。当正弦噪声注入电源时，LDO实现>20dB PSRR。

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A 0.55V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS

A 0.55V 100MHz LDO-embedded ADPLL is implemented in 65nm CMOS. A digitally-controlled relaxation oscillator (DCRXO) with a variable-threshold inverter and a digital calibration circuit is designed for robust start up under ultra-low supply voltage. A ΔΣ modulated pseudo-digital LDO provides a PVT-insensitive dithered internal voltage for the DCRXO. The 100MHz ADPLL including the LDO consumes a 67μW from a 0.55V supply and achieves the phase noise of -82.9dBc/Hz at 1MHz offset frequency. The LDO achieves >20dB PSRR when sinusoidal noise is injected to the supply.

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2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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