{"title":"具有冗余二进制数的分布式遗传算法并行处理器","authors":"T. Kamimura, A. Kanasugi","doi":"10.4156/IJIPM.VOL4.ISSUE1.12","DOIUrl":null,"url":null,"abstract":"Genetic algorithm (GA) is one of optimization algorithm based on an idea for evolution of life. GA can be applied various combination optimization problem. This paper proposes a parallel processor for distributed genetic algorithm (DGA) with redundant binary number. Since a redundant binary number has redundancy, solution expression becomes variegated. For this reason, it is expected the algorithm easily find the optimized solution, and the error rates decrease. Since DGA is a parallel algorithm, the performance can be improved by using a specified parallel processor. The effectiveness of the proposed processor was confirmed by some simulations and experiments using FPGA circuit board.","PeriodicalId":105832,"journal":{"name":"2012 6th International Conference on New Trends in Information Science, Service Science and Data Mining (ISSDM2012)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A parallel processor for distributed genetic algorithm with redundant binary number\",\"authors\":\"T. Kamimura, A. Kanasugi\",\"doi\":\"10.4156/IJIPM.VOL4.ISSUE1.12\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Genetic algorithm (GA) is one of optimization algorithm based on an idea for evolution of life. GA can be applied various combination optimization problem. This paper proposes a parallel processor for distributed genetic algorithm (DGA) with redundant binary number. Since a redundant binary number has redundancy, solution expression becomes variegated. For this reason, it is expected the algorithm easily find the optimized solution, and the error rates decrease. Since DGA is a parallel algorithm, the performance can be improved by using a specified parallel processor. The effectiveness of the proposed processor was confirmed by some simulations and experiments using FPGA circuit board.\",\"PeriodicalId\":105832,\"journal\":{\"name\":\"2012 6th International Conference on New Trends in Information Science, Service Science and Data Mining (ISSDM2012)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 6th International Conference on New Trends in Information Science, Service Science and Data Mining (ISSDM2012)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.4156/IJIPM.VOL4.ISSUE1.12\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 6th International Conference on New Trends in Information Science, Service Science and Data Mining (ISSDM2012)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4156/IJIPM.VOL4.ISSUE1.12","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A parallel processor for distributed genetic algorithm with redundant binary number
Genetic algorithm (GA) is one of optimization algorithm based on an idea for evolution of life. GA can be applied various combination optimization problem. This paper proposes a parallel processor for distributed genetic algorithm (DGA) with redundant binary number. Since a redundant binary number has redundancy, solution expression becomes variegated. For this reason, it is expected the algorithm easily find the optimized solution, and the error rates decrease. Since DGA is a parallel algorithm, the performance can be improved by using a specified parallel processor. The effectiveness of the proposed processor was confirmed by some simulations and experiments using FPGA circuit board.