{"title":"通过设计高性能的全硅化ESD器件来降低晶圆成本","authors":"K. Verhaege, C. Russ","doi":"10.1109/EOSESD.2000.890023","DOIUrl":null,"url":null,"abstract":"A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced. This novel design solution can be implemented in a straightforward manner without process modifications. ESD performance levels obtained in different 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economical silicon real estate consumption. In addition, a novel multi-finger turn-on design technique, which can be applied to both fully silicided and silicide blocked designs is presented.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":"{\"title\":\"Wafer cost reduction through design of high performance fully silicided ESD devices\",\"authors\":\"K. Verhaege, C. Russ\",\"doi\":\"10.1109/EOSESD.2000.890023\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced. This novel design solution can be implemented in a straightforward manner without process modifications. ESD performance levels obtained in different 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economical silicon real estate consumption. In addition, a novel multi-finger turn-on design technique, which can be applied to both fully silicided and silicide blocked designs is presented.\",\"PeriodicalId\":332394,\"journal\":{\"name\":\"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"32\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EOSESD.2000.890023\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EOSESD.2000.890023","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Wafer cost reduction through design of high performance fully silicided ESD devices
A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced. This novel design solution can be implemented in a straightforward manner without process modifications. ESD performance levels obtained in different 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economical silicon real estate consumption. In addition, a novel multi-finger turn-on design technique, which can be applied to both fully silicided and silicide blocked designs is presented.