{"title":"用递归结构实现离散余弦变换及其逆","authors":"Jiun-Lung Wang, Chung-Bin Wu, Bin-Da Liu, J. Yang","doi":"10.1109/SIPS.1999.822317","DOIUrl":null,"url":null,"abstract":"This paper discusses the recursive implementation of the discrete cosine transform (DCT) and its inverse (IDCT). The transform is constructed by using recursive filter structure to generate the transform kernel values. We first derive two trigonometric equations, which can be represented as the Chebyshev polynomial. Then we demonstrate that general length of the DCT and IDCT can be efficiently implemented by using the regressive structure derived from the recursive formulae. The computational complexity of each data throughput in these architectures is less than that in the conventional ones by as many as 50%. The proposed architectures are regular and suitable for parallel VLSI implementation.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"Implementation of the discrete cosine transform and its inverse by recursive structures\",\"authors\":\"Jiun-Lung Wang, Chung-Bin Wu, Bin-Da Liu, J. Yang\",\"doi\":\"10.1109/SIPS.1999.822317\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses the recursive implementation of the discrete cosine transform (DCT) and its inverse (IDCT). The transform is constructed by using recursive filter structure to generate the transform kernel values. We first derive two trigonometric equations, which can be represented as the Chebyshev polynomial. Then we demonstrate that general length of the DCT and IDCT can be efficiently implemented by using the regressive structure derived from the recursive formulae. The computational complexity of each data throughput in these architectures is less than that in the conventional ones by as many as 50%. The proposed architectures are regular and suitable for parallel VLSI implementation.\",\"PeriodicalId\":275030,\"journal\":{\"name\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.1999.822317\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.1999.822317","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of the discrete cosine transform and its inverse by recursive structures
This paper discusses the recursive implementation of the discrete cosine transform (DCT) and its inverse (IDCT). The transform is constructed by using recursive filter structure to generate the transform kernel values. We first derive two trigonometric equations, which can be represented as the Chebyshev polynomial. Then we demonstrate that general length of the DCT and IDCT can be efficiently implemented by using the regressive structure derived from the recursive formulae. The computational complexity of each data throughput in these architectures is less than that in the conventional ones by as many as 50%. The proposed architectures are regular and suitable for parallel VLSI implementation.