具有谐波抑制和基于dll的相位产生的d类级

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI:10.1109/MWSCAS.2012.6291953

J. Fritzin, B. Mesgarzadeh, A. Alvandpour

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引用次数: 1

摘要

本文提出了一种工作在2VDD(即2VDD)时具有三次谐波抑制的d类级。(额定电源电压的两倍)。基于dll的相位发生器用于产生驱动信号的相位，并且通过修改驱动级也可以抑制5次谐波。输出级和驱动器仅基于逆变器，其中在输出级消除了短路电流。在1 GHz工作时，模拟输出功率为+19.4 dBm，使用1 v电源和5-Ω负载，漏极效率(DE)和功率附加效率(PAE)分别为72%和52%，其中包括基于dll的相位发生器和驱动器的功耗。与传统的d类级相比，三次谐波被抑制23 dB (-33 dBc)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Class-D stage with harmonic suppression and DLL-based phase generation

This paper presents a Class-D stage with 3rd harmonic suppression operating at 2VDD(i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Ω load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.

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2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

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