Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes

For over forty years, DRAM has been the most compelling choice for main memory. It is a well understood commodity technology that strikes an ideal balance between cost, performance, capacity and energy. Yet, as DRAM scales to the extremes of deep submicron technology, it faces a critical challenge with the impact of process variation (PV) on chip yield: PV in the transistor and capacitor used to hold a bit of information, along with other components, can cause critical requirements to be violated, including retention capability, cell reliability and operational timing. The challenges of retention and reliability are well known. However, the latter challenge has received significantly less attention---the impact of operational timing violations due to PV on DRAM yield. This challenge stands as an equal to the others in achieving sufficient yield for continued commodity production of DRAM. In this paper, we argue that timing requirements must be relaxed and exposed on a per-location basis for management by the memory sub-system architecture to overcome the challenge to yield from timing. This "soft yield" approach trades exposed timing variability for enhanced yield, without harming chip density. Because relaxing and exposing variable timing can lead to application performance loss, a suite of techniques must be developed by the architecture community to mitigate the loss. We raise awareness of this problem and suggest directions where solutions may be found.