电源轨逻辑:用于数字砷化镓电路的低功耗逻辑样式

Proceedings of 1994 IEEE GaAs IC Symposium Pub Date : 1994-10-16 DOI:10.1109/GAAS.1994.636925

A. Chandna, Richard B. Brown, D. Putti, C. Kibler

{"title":"电源轨逻辑:用于数字砷化镓电路的低功耗逻辑样式","authors":"A. Chandna, Richard B. Brown, D. Putti, C. Kibler","doi":"10.1109/GAAS.1994.636925","DOIUrl":null,"url":null,"abstract":"This paper describes a new logic style called Power Rail Logic (PRL) which is compatible with DCFL circuits. Multiplexors, latches, flip-flops and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-bit barrel shifters designed in DCFL and in PRL, were successfully fabricated and tested. Test results are given for both circuits.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Power rail logic: a low power logic style for digital GaAs circuits\",\"authors\":\"A. Chandna, Richard B. Brown, D. Putti, C. Kibler\",\"doi\":\"10.1109/GAAS.1994.636925\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a new logic style called Power Rail Logic (PRL) which is compatible with DCFL circuits. Multiplexors, latches, flip-flops and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-bit barrel shifters designed in DCFL and in PRL, were successfully fabricated and tested. Test results are given for both circuits.\",\"PeriodicalId\":328819,\"journal\":{\"name\":\"Proceedings of 1994 IEEE GaAs IC Symposium\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE GaAs IC Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1994.636925\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1994.636925","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

本文介绍了一种与DCFL电路兼容的电源轨道逻辑(Power Rail logic, PRL)。多路复用器、锁存器、触发器和异或门可以使用这种逻辑风格来构建。与DCFL相比，PRL使用更少的晶体管，具有更大的噪声裕度，并且功耗延迟产品降低高达40%。在DCFL和PRL中设计了一个包含32位桶形移位器的测试芯片，并成功地进行了测试。给出了两种电路的测试结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Power rail logic: a low power logic style for digital GaAs circuits

This paper describes a new logic style called Power Rail Logic (PRL) which is compatible with DCFL circuits. Multiplexors, latches, flip-flops and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-bit barrel shifters designed in DCFL and in PRL, were successfully fabricated and tested. Test results are given for both circuits.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of 1994 IEEE GaAs IC Symposium

自引率

0.00%

发文量