在体系结构级别并发错误检测

Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210) Pub Date : 1998-12-02 DOI:10.1109/ISSS.1998.730600

C. Bolchini, W. Fornaciari, F. Salice, D. Sciuto

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引用次数: 6

摘要

介绍了一种具有并发错误检测能力的系统设计方法。该方法由功能体系结构和检查体系结构组成，用于验证功能体系结构计算的数据。该方法通过硬件资源和数据共享分别减少了冗余和延迟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Concurrent error detection at architectural level

A methodology for designing systems with concurrent error detection capability is introduced. The proposed approach consists of a functional architecture and a checking architecture to verify data computed by the functional one. The methodology reduces both redundancy and latency through hardware resources and data sharing, respectively.

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来源期刊

Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210)

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