{"title":"计算沃尔什系数的硬件","authors":"Y. Iguchi, Tsutomu Sasao","doi":"10.1109/ISMVL.2005.19","DOIUrl":null,"url":null,"abstract":"This paper presents a method to compute a fragment of the Walsh coefficients of logic functions using hardware. First, it introduces the Walsh transformation tree, and shows a method to compute Walsh coefficients using the Walsh transformation tree. Next, it shows the hardware realization for the Walsh tree. The amount of hardware to compute a coefficient and the entire coefficients are O(2/sup n/) and O(n/sup 2//spl middot/2/sup n/), respectively. FPGA implementations show their feasibility up to n=14. The FPGA realization is at least 1253 times faster than a software implementation on a microprocessor for n=14.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Hardware to compute Walsh coefficients\",\"authors\":\"Y. Iguchi, Tsutomu Sasao\",\"doi\":\"10.1109/ISMVL.2005.19\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a method to compute a fragment of the Walsh coefficients of logic functions using hardware. First, it introduces the Walsh transformation tree, and shows a method to compute Walsh coefficients using the Walsh transformation tree. Next, it shows the hardware realization for the Walsh tree. The amount of hardware to compute a coefficient and the entire coefficients are O(2/sup n/) and O(n/sup 2//spl middot/2/sup n/), respectively. FPGA implementations show their feasibility up to n=14. The FPGA realization is at least 1253 times faster than a software implementation on a microprocessor for n=14.\",\"PeriodicalId\":340578,\"journal\":{\"name\":\"35th International Symposium on Multiple-Valued Logic (ISMVL'05)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"35th International Symposium on Multiple-Valued Logic (ISMVL'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2005.19\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2005.19","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a method to compute a fragment of the Walsh coefficients of logic functions using hardware. First, it introduces the Walsh transformation tree, and shows a method to compute Walsh coefficients using the Walsh transformation tree. Next, it shows the hardware realization for the Walsh tree. The amount of hardware to compute a coefficient and the entire coefficients are O(2/sup n/) and O(n/sup 2//spl middot/2/sup n/), respectively. FPGA implementations show their feasibility up to n=14. The FPGA realization is at least 1253 times faster than a software implementation on a microprocessor for n=14.
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