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引用次数: 0
摘要
所讨论的直接序列扩频(DSSS)通信系统要想取得成功,需要在接收机中进行精确的载波恢复和相位估计。本文提出了一种模拟DDC-CRL,它既具有上述两种功能,又具有理想的DSSS接收机所具有的扩频、解调和位检测操作。本文提出的DDC-CRL以高达1.53 Mbps的比特率运行,并适应任意序列长度。该环路可在2.4 GHz至2.4835 GHz ISM(工业、科学和医疗)频段内超过20 MHz带宽的任何地方运行。DDC-CRL是为奥地利微系统公司(AMS)的0.35 μ m CMOS工艺设计的。
CMOS based decision directed costas carrier recovery loop (DDC-CRL) for a DSSS communication system
For the discussed DSSS (direct sequence spread spectrum) communication system to be successful, accurate carrier recovery and phase estimation are required in the receiver. This paper presents an analogue DDC-CRL which performs both of these functions as well as the despreading, demodulation and bit detection operations performed by an ideal DSSS receiver. The DDC-CRL presented in this paper operates at bit rates up to 1.53 Mbps and accommodates arbitrary sequence length. The loop operates anywhere over a 20 MHz bandwidth within the 2.4 GHz to 2.4835 GHz ISM (industrial, scientific and medical) band. The DDC-CRL is designed for the 0.35 mum CMOS process from Austria Microsystems (AMS).